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An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS
Ma,Xiaofei1,2,3; Lu,Yan2,4; Li,Qiang1; Ki,Wing Hung5; Martins,Rui P.2,4,6
2020-11-01
Source PublicationIEEE Transactions on Circuits and Systems I: Regular Papers
ISSN1549-8328
Volume67Issue:11Pages:4041-4052
AbstractThis paper presents an NMOS digital low-dropout regulator (LDO) with fast transient response and ultra-low quiescent current, to provide a tunable power supply for near-threshold voltage computing circuits in internet-of-things (IoT) devices. An LDO with an NMOS power transistor can enjoy the intrinsic fast transient response of the source-follower-like power stage, contributing to the proportional (P) part of the control loop. A shift-register-based digital control serves as an excellent candidate for the integral (I) part of the control loop. In addition, we propose a NAND-gate-based high-pass analog path (NAP) as the derivative (D) part of the loop, making the whole control scheme a complete PID control, therefore, achieving a fast transient response. We fabricated two versions of the prototype chip, one with a 35 pF on-chip load capacitor and a fast-transient on-chip load, and the other with no load capacitor, in 28-nm CMOS. The proposed NMOS digital LDO with NAP can handle the load transient of 160 mA/ns with 810-nA quiescent current, achieving 117-mV voltage undershoot. With the proposed techniques, we can achieve nearly two orders of better FoM when comparing it to the state-of-the-art works.
KeywordAnalog assisted (AA) coarse/fine tuning digital control digital low-dropout regulator (LDO) fully integrated voltage regulator (FIVR) limit cycle oscillation (LCO) NMOS LDO nonlinear control output-capacitor-free
DOI10.1109/TCSI.2020.3009454
URLView the original
Language英语
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Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Corresponding AuthorLu,Yan
Affiliation1.Institute of Integrated Circuits and Systems,University of Electronic Science and Technology of China,Chengdu,610054,China
2.State Key Laboratory of Analog and Mixed-Signal,VLSI,University of Macau,Macao
3.Department of Electronic and Computer Engineering,Hong Kong University of Science and Technology,Hong Kong
4.FST-DECE,University of Macau,Macao
5.Department of Electronic and Computer Engineering,Hong Kong University of Science and Technology,Hong Kong
6.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,1049-001,Portugal
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Ma,Xiaofei,Lu,Yan,Li,Qiang,et al. An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2020,67(11):4041-4052.
APA Ma,Xiaofei,Lu,Yan,Li,Qiang,Ki,Wing Hung,&Martins,Rui P..(2020).An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS.IEEE Transactions on Circuits and Systems I: Regular Papers,67(11),4041-4052.
MLA Ma,Xiaofei,et al."An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS".IEEE Transactions on Circuits and Systems I: Regular Papers 67.11(2020):4041-4052.
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