UM
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler
Jiang,Wenning1; Zhu,Yan1; Chan,Chi Hang1; Murmann,Boris2; Martins,Rui Paulo1
2021-02-01
Source PublicationIEEE Transactions on Circuits and Systems I: Regular Papers
ISSN1549-8328
Volume68Issue:2Pages:557-568
AbstractThis paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rd Nyquist zone. The converter's front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers' inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC's power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step.
KeywordAnalog-to-digital converter background timing skew calibration current integrating sampler SAR ADC time-interleaved ADC timing skew
DOI10.1109/TCSI.2020.3039252
URLView the original
Language英语
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Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.State Key Laboratory of Analog and Mixed Signal VLSI,Institute of Microelectronics,University of Macau,Macao
2.Department of Electrical Engineering,Stanford University,Stanford,United States
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Jiang,Wenning,Zhu,Yan,Chan,Chi Hang,et al. A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2021,68(2):557-568.
APA Jiang,Wenning,Zhu,Yan,Chan,Chi Hang,Murmann,Boris,&Martins,Rui Paulo.(2021).A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler.IEEE Transactions on Circuits and Systems I: Regular Papers,68(2),557-568.
MLA Jiang,Wenning,et al."A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler".IEEE Transactions on Circuits and Systems I: Regular Papers 68.2(2021):557-568.
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