UM
A Fully Integrated FVF LDO with Enhanced Full-Spectrum Power Supply Rejection
Cai,Guigang1,2; Lu,Yan1; Zhan,Chenchang2,3; Martins,Rui P.1,4
2021-04-01
Source PublicationIEEE Transactions on Power Electronics
ISSN0885-8993
Volume36Issue:4Pages:4326-4337
AbstractThis article presents a fully integrated flipped voltage follower (FVF) based low-dropout (LDO) regulator with enhanced full-spectrum power supply rejection (PSR) and unity-gain bandwidth over 400MHz for noise-sensitive circuits. Following the study of three types of FVF LDO's PSR performances, we propose a novel FVF LDO with a low-gain fast loop-1 and a high-gain slow loop-2. In prior FVF LDOs, their PSRs are either full-spectrum, or not, but with low PSR at low frequency. In this article, we fully utilize both dc gains of loop-1 and loop-2 for the low-frequency PSR, while the high-frequency PSR remains unchanged. In addition, we use dynamic compensation to push the loop-2's UGB to higher frequency for a better PSR bandwidth. This work, fabricated in 65 nm complementary metal oxide semiconductor (CMOS), with 1.2-V input and 1-V output, exhibits a measured quiescent current (IQ) varying from 27 to 82 μA for a load current ILOAD between 5 μA and 20 mA. The circuit achieves a low frequency PSR of-58 dB with the worst full-spectrum PSR of-9 dB in 20 mA ILOAD with a 300 pF on-chip output capacitor. Further, with an UGB over 400 MHz, the proposed FVF LDO reaches 0.9 ns response time when ILOAD changes between 100 μA and 20 mA with edge times less than 0.8 ns.
KeywordFlipped voltage follower (FVF) full-spectrum power supply rejection (PSR) fully-integrated low-dropout (LDO) low-dropout regulator (LDO) PSR
DOI10.1109/TPEL.2020.3024595
URLView the original
Language英语
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Document TypeJournal article
CollectionUniversity of Macau
Corresponding AuthorLu,Yan
Affiliation1.State Key Laboratory of Analog and Mixed-Signal Vlsi,Institute of Microelectronics,FST-DECE,University of Macau,Macao
2.School of Microelectronics,Southern University of Science and Technology,Shenzhen,China
3.Engineering Research Center of Integrated Circuits for Next-Generation Communications,Ministry of Education,Beijing,100816,China
4.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,1049-001,Portugal
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Cai,Guigang,Lu,Yan,Zhan,Chenchang,et al. A Fully Integrated FVF LDO with Enhanced Full-Spectrum Power Supply Rejection[J]. IEEE Transactions on Power Electronics,2021,36(4):4326-4337.
APA Cai,Guigang,Lu,Yan,Zhan,Chenchang,&Martins,Rui P..(2021).A Fully Integrated FVF LDO with Enhanced Full-Spectrum Power Supply Rejection.IEEE Transactions on Power Electronics,36(4),4326-4337.
MLA Cai,Guigang,et al."A Fully Integrated FVF LDO with Enhanced Full-Spectrum Power Supply Rejection".IEEE Transactions on Power Electronics 36.4(2021):4326-4337.
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