UM
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization
Wang,Wei; Chan,Chi Hang; Zhu,Yan; Martins,Rui P.
2020-06-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume55Issue:6Pages:1588-1598
AbstractThis article reports a 4th-order 100-MHz bandwidth continuous-time (CT) delta-sigma modulator in 28-nm CMOS. A preliminary sampling and quantization (PSQ) technique is presented, which allows almost a full utilization of the clock period for the quantization to extend the available conversion time of the backend quantizer (QTZ) under a 0.65 excess loop delay (ELD) coefficient. With the PSQ, both the sampling and quantization of the backend QTZ are splitted into two steps, coarse and fine, similar to the subranging architecture to save power. The QTZ runs at 2 GHz achieving 7 bit (1 b error correction) with only 1.4-mW power. By adding a feedforward ELD compensation path in the cascade of integrators of the cascade of integrators in feedforward (CIFF) topology, only one digital-to-analog converter (DAC) is necessary in this design. The modulator attains a signal bandwidth of 100 MHz with 72.6-dB signal-to-noise and distortion ratio (SNDR) while only consuming 16.3 mW from 1.1- and 1.5-V power supplies. The prototype has a dynamic range of 76.3 dB and a Schreier FoM of 174.2 dB with an active area of 0.019 mm
KeywordAnalog-to-digital conversion (ADC) continuous-time delta-sigma modulator (CT-DSM) preliminary sampling and quantization (PSQ) technique single amplifier biquad (SAB) successiveapproximation-register (SAR) architecture-based quantizer (QTZ)
DOI10.1109/JSSC.2020.2978384
URLView the original
Language英語English
Scopus ID2-s2.0-85082520650
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Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
AffiliationDepartment of Electrical and Computer Engineering,State Key Laboratory of Analog and Mixed-Signal VLSI,Faculty of Science and Technology,Institute of Microelectronics,University of Macau,999078,Macao
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Wang,Wei,Chan,Chi Hang,Zhu,Yan,et al. A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization[J]. IEEE Journal of Solid-State Circuits,2020,55(6):1588-1598.
APA Wang,Wei,Chan,Chi Hang,Zhu,Yan,&Martins,Rui P..(2020).A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization.IEEE Journal of Solid-State Circuits,55(6),1588-1598.
MLA Wang,Wei,et al."A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization".IEEE Journal of Solid-State Circuits 55.6(2020):1588-1598.
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