60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration
Alternative TitleExpression Profiling and Localization Analysis of Parkinson’s Disease Associated Protein LRRK2
Chan, Chi-Hang; Zhu, Yan; Li, Cheng; Zhang, Wai-Hong; Ho, Iok-Meng; Wei, Lai; Seng-Pan, U.; Martins, Rui Paulo
2017-10
Source PublicationIEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN0018-9200
Volume52Issue:10Pages:2576-2588
Abstract

This paper presents a reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a reference error often occurs in high-speed SAR ADCs due to the signal dependent fast switching transient, and leads to a large differential nonlinearity and missing codes, eventually degrading conversion accuracy. The calibration concept aims to differentiate the error outputs and correct them by simply performing a subtraction in the digital domain. It runs in the background with a little hardware overhead, and does not depend on the type of the input signal or reduce the dynamic range. Two prototypes were measured which are made up of different reference generation circuits. Design #1 has the reference voltage from off-chip and a 3-pF decoupling capacitor on-chip, while design #2 includes an on-chip reference buffer. Both designs were fabricated in 65-nm CMOS and achieve at least 9-dB improvement on signal-to-(Noise + Distortion) ratio (SNDR) after calibration. The total core area is around 0.012 mm(2) for both chips and the Nyquist SNDR of designs #1 and #2 is 59.03 and 57.93 dB, respectively.

KeywordReference Buffer Reference Error Calibration Successive Approximation Register (Sar) Analog-to-digital Converter (Adc) Threshold Reconfigurable Comparator
DOI10.1109/JSSC.2017.2728784
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000411835400007
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
Fulltext Access
Citation statistics
Cited Times [WOS]:17   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INSTITUTE OF MICROELECTRONICS
Corresponding AuthorChan, Chi-Hang
AffiliationDepartment of ECE, Faculty of Science and Technology, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Chan, Chi-Hang,Zhu, Yan,Li, Cheng,et al. 60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS,2017,52(10):2576-2588.
APA Chan, Chi-Hang.,Zhu, Yan.,Li, Cheng.,Zhang, Wai-Hong.,Ho, Iok-Meng.,...&Martins, Rui Paulo.(2017).60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration.IEEE JOURNAL OF SOLID-STATE CIRCUITS,52(10),2576-2588.
MLA Chan, Chi-Hang,et al."60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration".IEEE JOURNAL OF SOLID-STATE CIRCUITS 52.10(2017):2576-2588.
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