A process-insensitive current-controlled delay generator with threshold voltage compensation
Wei H.-G.1; Chio U.-F.1; Sin S.-W.1; U S.-P.1; Martins R.P.1,2
2010-12-01
Conference Name2010 IEEE Asian Solid-State Circuits Conference
Source Publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages221-224
Conference Date8-10 Nov. 2010
Conference PlaceBeijing, China
Abstract

A process-insensitive current-controlled delay generator is presented with a large tunable range of the time delay. By adopting process variation compensation techniques in the generation of time delay, the delay generator is able to provide process-insensitive clock pulses. The circuit has been fabricated in 90nm CMOS technology, consumes 310μW from a 1.1V supply. Using, in a typical case, 20μA of reference current, it can generate a delay of 2.36 ns. The delay variation observed in 14 measured chips has shown a standard deviation of 1.24%. ©2010 IEEE.

DOI10.1109/ASSCC.2010.5716595
URLView the original
Language英语
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Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Affiliation1.Analog and Mixed Signal VLSI Laboratory, Faculty of Science and Technology, University of Macau, Macao, China
2.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Wei H.-G.,Chio U.-F.,Sin S.-W.,et al. A process-insensitive current-controlled delay generator with threshold voltage compensation[C],2010:221-224.
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