An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H
Sin S.-W.1; Ding L.1; Zhu Y.1; Wei H.-G.1; Chan C.-H.1; Chio U.-F.1; Seng-Pan U.1; Martins R.P.1,2; Maloberti F.1,3
Conference NameESSCIRC 2010 - 36th European Solid State Circuits Conference
Source Publication2010 Proceedings of ESSCIRC
Conference Date14-16 Sept. 2010
Conference PlaceSeville, Spain

An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and subthreshold operation enables the use of a power-effective, single-stage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step. ©2010 IEEE.

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Document TypeConference paper
Faculty of Science and Technology
Affiliation1.Analog and Mixed Signal VLSI Laboratory ,Faculty of Science and Technology, University of Macau, Macao, China
2.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
3.University of Pavia, Italy
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Sin S.-W.,Ding L.,Zhu Y.,et al. An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H[C],2010:218-221.
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