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A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration
Chio U.-F.2; Chan C.-H.2; Choi H.-L.2; Sin S.-W.2; Seng-Pan U.2; Martins R.P.1,2
2011-12-12
Conference NameEuropean Solid-State Circuits Conference
Source Publication2011 Proceedings of the ESSCIRC (ESSCIRC)
Pages363-366
Conference Date12-16 Sept. 2011
Conference PlaceHelsinki, Finland
Abstract

This paper reports a 7-bit 300-MS/s subranging ADC fabricated in standard 65nm CMOS, which utilizes embedded reference and gain loss error calibration techniques. A shared passive capacitive DAC array performs the input sampling in quantization mode and reference generation in calibration mode, providing a linear, accurate and compact calibration implementation. As a consequence of the developed calibration techniques, uniform-sized dynamic comparators are employed to reduce the process-mismatch variation and nonlinearity error, when compared with the conventional structures. The ADC achieves peak SNDR of 40.5dB at 300MS/s and 39dB at 400MS/s, with ERBW of 300MHz and 350MHz, respectively. The power consumption is 2.3mW only from 1.2-V supply at 300MS/s. © 2011 IEEE.

DOI10.1109/ESSCIRC.2011.6044982
URLView the original
Language英语
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Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Instituto Superior Técnico
2.Universidade de Macau
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chio U.-F.,Chan C.-H.,Choi H.-L.,et al. A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration[C],2011:363-366.
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