A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC | |
Yan Zhu1![]() ![]() ![]() ![]() ![]() | |
2012-09-28 | |
Conference Name | 2012 Symposium on VLSI Circuits (VLSIC) |
Source Publication | 2012 Symposium on VLSI Circuits Digest of Technical Papers |
Pages | 90-91 |
Conference Date | 13-15 June 2012 |
Conference Place | Honolulu, HI, USA |
Abstract | A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2 . |
DOI | http://doi.org/10.1109/VLSIC.2012.6243804 |
URL | View the original |
Indexed By | 其他 |
Language | 英语 |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | INSTITUTE OF MICROELECTRONICS Faculty of Science and Technology DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Affiliation | 1.State-Key Laboratory of Analog and Mixed Signal VLSI, FST, University of Macau, Macao, China 2.Also with Synopsys - Chipidea Microelectronics (Macau) Limited 3.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal |
First Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Yan Zhu,Chi-Hang Chan,Sai-Weng Sin,et al. A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC[C],2012:90-91. |
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