A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array
Wen-Lan Wu1; Sai-Weng Sin1; Seng-Pan U1,2; Rui Paulo Martins1,3
2012
Conference NameIEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Source Publication2012 IEEE Asia Pacific Conference on Circuits and Systems
Pages268-271
Conference DateDEC 02-05, 2012
Conference PlaceKaohsiung, TAIWAN
Abstract

A novel switching method is proposed and implemented in a 10-bit fully differential SAR ADC. When compared with the charge recycling or the set-and-down approach, the proposed scheme uses a single-ended switching procedure to reduce the total switching energy by 80% or 20%, respectively. Besides, two redundant decisions are inserted in the SAR ADC with a 4b/4b/4b configuration, which is capable of more than 30% speed enhancement. The 10-bit SAR ADC’s performance is verified through Matlab simulation and it achieves 10-b resolution. After a Monte-Carlo analysis (100- times), the mean value of the SNDR is 61.8dB, and the maximum INL and DNL are 0.05LSB and 0.1LSB, respectively.

DOI10.1109/APCCAS.2012.6419023
URLView the original
Indexed BySCIE
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000316598900068
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Citation statistics
Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI Faculty of Science and Technology, University of Macau, Macao, China
2.Also with Synopsys - Chipidea Microelectronics (Macau) Limited
3.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Wen-Lan Wu,Sai-Weng Sin,Seng-Pan U,et al. A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array[C],2012:268-271.
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