Split-based time-interleaved ADC with digital background timing-skew calibration
Guo M.3; Sin S.-W.3; Seng-Pan U.1; Martins R.P.2
2017-07-10
Conference Name13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Source Publication2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Pages113-116
Conference DateJUN 12-15, 2017
Conference PlaceGiardini Naxos, Italy
Abstract

This paper presents a split-based time-interleaved (TI) ADC with digital background timing calibration for wideband applications. Each interleaved channel uses a split ADC, which adds a dimension for timing-skew error detection and correction. Thus, the complexity of digital post-processing is greatly relaxed without the use of any dummy channel. The behavioral simulations show a 28 dB and 35 dB improvements in signal-to-noise plus distortion (SNDR) and spurious-free dynamic range (SFDR) respectively, after adopting the proposed timing skew correction for a 10-bit 4GS/s ADC example.

KeywordAdc Converters Digital Background Calibration Split-adc Time-interleaving Timing
DOIhttp://doi.org/10.1109/PRIME.2017.7974120
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000426907000029
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Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Synopsys Macau Ltd
2.Instituto Superior Técnico
3.Universidade de Macau
Recommended Citation
GB/T 7714
Guo M.,Sin S.-W.,Seng-Pan U.,et al. Split-based time-interleaved ADC with digital background timing-skew calibration[C],2017:113-116.
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