UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-10 of 74 Help

Filters                                
Selected(0)Clear Items/Page:    Sort:
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:23/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, November 6-8, 2017
Authors:  Wei Wang;  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U.;  Rui Paulo Martins
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
A Digital PWM Controlled KY Step-Up Converter Based on Frequency Domain ΣΔ ADC Conference paper
IEEE International Symposium on Industrial Electronics, Edinburgh, UK, JUN 18-21, 2017
Authors:  Xia Du;  Chi-Seng Lam;  Sai-Weng Sin;  Man-Kay Law;  Franco Maloberti;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/12/23
Frequency Domain Sigma-delta Adc  Ky Converter  Digital Control  
A Digital PWM Controlled KY Step-Up Converter based on Passive Sigma-Delta Modulator Conference paper
2017 IEEE 3rd International Future Energy Electronics Conference and ECCE Asia, IFEEC - ECCE Asia 2017, Kaohsiung, Taiwan, JUN 03-07, 2017
Authors:  Xia Du;  Chi-Seng Lam;  Sai-Weng Sin;  Franco Maloberti;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:7/0  |  Submit date:2018/12/23
Digital Control  Ky Converter  Sigma-delta Modulator  
A sub-1V 78-nA bandgap reference with curvature compensation Journal article
MICROELECTRONICS JOURNAL, 2017,Volume: 63,Page: 35-40
Authors:  Ziyang Luo;  Yan Lu;  Mo Huang;  Junmin Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:22/0  |  Submit date:2018/10/30
Bandgap Reference  Cmos Analog Integrated Circuits  Internet-of-things (Iot)  Ultra-low Power  Curvature Compensation  Temperature Coefficient  
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/11/06
An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Mo Huang;  Yan Lu;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:8/0  |  Submit date:2018/11/06
A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United states, 5-9 Feb. 2017
Authors:  Mo Huang;  Yan Lu;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:9/0  |  Submit date:2018/11/06
A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United states, 5-9 Feb. 2017
Authors:  Jiang, Junmin;  Lu, Yan;  Ki, Wing-Hung;  Seng-Pan, U.;  Martins, Rui P.
Favorite  |  View/Download:9/0  |  Submit date:2018/11/06
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)