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A Digital PWM Controlled KY Step-Up Converter Based on Frequency Domain ΣΔ ADC Conference paper
IEEE International Symposium on Industrial Electronics, Edinburgh, UK, JUN 18-21, 2017
Authors:  Xia Du;  Chi-Seng Lam;  Sai-Weng Sin;  Man-Kay Law;  Franco Maloberti;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/12/23
Frequency Domain Sigma-delta Adc  Ky Converter  Digital Control  
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:22/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
A Digital PWM Controlled KY Step-Up Converter based on Passive Sigma-Delta Modulator Conference paper
2017 IEEE 3rd International Future Energy Electronics Conference and ECCE Asia, IFEEC - ECCE Asia 2017, Kaohsiung, Taiwan, JUN 03-07, 2017
Authors:  Xia Du;  Chi-Seng Lam;  Sai-Weng Sin;  Franco Maloberti;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:7/0  |  Submit date:2018/12/23
Digital Control  Ky Converter  Sigma-delta Modulator  
A sub-1V 78-nA bandgap reference with curvature compensation Journal article
MICROELECTRONICS JOURNAL, 2017,Volume: 63,Page: 35-40
Authors:  Ziyang Luo;  Yan Lu;  Mo Huang;  Junmin Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:22/0  |  Submit date:2018/10/30
Bandgap Reference  Cmos Analog Integrated Circuits  Internet-of-things (Iot)  Ultra-low Power  Curvature Compensation  Temperature Coefficient  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)  
A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller Conference paper
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, JAPAN, 7-9 Nov. 2016
Authors:  Yuan Ren;  Sai-Weng Sin;  Chi-Seng Lam;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/12/23
Multi-channel Sigma Delta Front-end Interface  Programmable-gain  Integrated Pe Controller  
Metastablility in SAR ADCs Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Boris Murmann;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:14/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Comparator  Metastability  Successive Approximation Register (Sar)  
A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 166-170
Authors:  Lu, Yan;  Dai, Haojuan;  Huang, Mo;  Law, Man-Kay;  Sin, Sai-Weng;  U, Seng-Pan;  Martins, Rui P.
Favorite  |  View/Download:19/0  |  Submit date:2018/10/30
Cmos Rectifier  Cross-connected (Cc) Rectifier  Rf Energy Harvesting  Ultrahigh Frequency (Uhf)  Wireless Power Transfer (Wpt)  
Active-Passive Delta Sigma Modulator for High-Resolution and Low-Power Applications Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 364-374
Authors:  Hussain, Arshad;  Sin, Sai-Weng;  Chan, Chi-Hang;  U, Seng-Pan (Ben);  Maloberti, Franco;  Martins, Rui P.
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Delta-Sigma Modulator (Delta Sigma m)  Discrete Time (Dt)  Low-gain-amplifier-based Switched-capacitor (Sc) Integrator  Noise Shaping  Passive Sc Integrator  
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11