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A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 12,Page: 2979-2991
Authors:  Yin J.;  Mak P.-I.;  Maloberti F.;  Martins R.P.
Favorite  |  View/Download：10/0  |  Submit date：2019/02/11
1/f3 Phase Noise Corner  Divided Output  Flicker Noise  Impulse Sensitivity Function (Isf)  Phase Combiner  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Supply Voltage  Time-interleaved (Ti).  
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download：13/0  |  Submit date：2019/02/11
A μNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration With a Digital Microfluidic Device Inside a Portable Magnet Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 10,Page: 2274-2286
Authors:  Ka-Meng Lei;  Pui-In Mak;  Man-Kay Law;  Rui P. Martins
Favorite  |  View/Download：18/0  |  Submit date：2019/02/11
Avidin  Baseband  Biological  Chemical  Cmos  Digital Microfluidic (Dmf)  Electronic Automation  Filter  Low-noise Amplifier (Lna)  Magnetic Sensing  Nuclear Magnetic Resonance (Nmr)  Point-of-care  Power Amplifier (Pa)  Radio Frequency (Rf)  Receiver (Rx)  Transceiver (Trx)  Transmitter (Tx)  
CMOS biosensors for in vitro diagnosis–transducing mechanisms and applications Journal article
Lab on a Chip, 2016,Volume: 16,Issue: 19,Page: 3664-3681
Authors:  Ka-Meng Lei;  Pui-In Mak;  Man-Kay Law;  Rui P. Martins
Favorite  |  View/Download：5/0  |  Submit date：2019/03/05
Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016,Volume: 63,Issue: 9,Page: 903-907
Authors:  Huang M.;  Lu Y.;  Sin S.-W.;  Seng P.;  Martins R.P.;  Ki W.-H.
Favorite  |  View/Download：7/0  |  Submit date：2019/02/11
Compensation Zero  Describing Function  Digital Control  Feedforward Path  Limit Cycle Oscillation (Lco)  Low Dropout Regulator (Ldo)  Sampled Nonlinear System  
A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM Conference paper
2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 22-25 May 2016
Authors:  Chee-Cheow Lim;  Harikrishnan Ramiah;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download：7/0  |  Submit date：2019/02/11
Inductor  Rfic  Vco  Dual-layer Patterned Floating Shield  
A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016,Volume: 63,Issue: 7,Page: 683-687
Authors:  Huang M.;  Lu Y.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download：6/0  |  Submit date：2019/02/11
Burst Mode  Coarse-fine-tuning (Cft)  Digital Control  Dynamic Voltage Scaling (Dvs)  Energy-efficient Digital  Fast Transient  Low Dropout Regulator (Ldo)  
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download：8/0  |  Submit date：2019/02/11
Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
A 1.1 μW CMOS smart temperature sensor with an inaccuracy of ±0.2 °C (3σ) for clinical temperature monitoring Journal article
IEEE Sensors Journal, 2016,Volume: 16,Issue: 8,Page: 2272-2281
Authors:  Man-Kay Law;  Sanfeng Lu;  Tao Wu;  Amine Bermak;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download：8/0  |  Submit date：2019/02/11
Smart Temperature Sensor  Ultra-low Power  High Accuracy  Incremental Analog-to-digital Converter (I-adc),  Multi-ratio Pre-gain  Block-based Data Weighted Averaging (Bdwa)  
A 2-μW 45-nV/√Hz Readout Front End with Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016,Volume: 63,Issue: 4,Page: 351-355
Authors:  Jiangchao Wu;  Man-Kay Law;  Pui-In Mak;  Rui P. Martins
Favorite  |  View/Download：11/0  |  Submit date：2019/02/11
Capacitively Coupled Instrumentation Amplifier (Ccia)  Dc Servo Loop (Dsl)  Multiple Chopping  Neural Recording Front End  Pseudofeedback Amplifier  Ripple Reduction Loop (Rrl)