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A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Guohe Yin;  He-Gong Wei;  U–Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
Analgo-to-digital Converter  Successive Approximation Register  Ultra-low Power  Sensor Applications  
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
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Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
A 22.4 μw 80dB SNDR ΣΔ modulator with passive analog adder and SAR quantizer for EMG application Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors:  Zhijie Chen;  Yang Jiang;  Chenyan Cai;  He-Gong Wei;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Σδ Modulator  Sar Quantizer  Passive Analog Adder