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Accuracy-enhanced variance-based time-skew calibration using SAR as window detector
Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:
Liu J.
;
Chan C.-H.
;
Sin S.-W.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:33/0
|
TC[WOS]:
2
TC[Scopus]:
2
|
Submit date:2019/02/13
Bandwidth mismatches
split-digital to analog converter (DAC)
successive-approximation-register (SAR) analog-to-digital converter (ADC)
time-interleaved (TI)
variance based
window detector (WD)
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:
Xing D.
;
Zhu Y.
;
Chan C.-H.
;
Maloberti F.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:23/0
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2019/02/11
reference interference
SAR ADC
time-interleaved scheme
two-step SAR conversion
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler
Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:
Jiang W.
;
Zhu Y.
;
Chan C.-H.
;
Murmann B.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:12/0
|
TC[WOS]:
0
TC[Scopus]:
2
|
Submit date:2019/02/11
background calibration
current integrating sampler
Time-interleaved ADC
timing skew
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 11,Page: 2279-2289
Authors:
Wang, Guan Cheng
;
Zhu, Yan
;
Chan, Chi-Hang
;
Seng-Pan, U.
;
Martins, Rui P.
Favorite
|
View/Download:19/0
|
TC[WOS]:
0
TC[Scopus]:
1
|
Submit date:2019/01/17
Bridge digital-to-analog converter (DAC)
gain error calibration
successive approximation register (SAR)
analog-to-digital converters (ADCs)
testing signal generation (TSG)
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS
Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:
Wang B.
;
Sin S.-W.
;
Seng-Pan U.
;
Malobertr F.
;
Martins R.P.
Favorite
|
View/Download:19/0
|
TC[WOS]:
0
TC[Scopus]:
5
|
Submit date:2019/02/11
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems
Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Authors:
Mao F.
;
Lu Y.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:13/0
|
TC[WOS]:
0
TC[Scopus]:
2
|
Submit date:2019/02/11
delay compensation
feedback loop
implantable medical devices
real time
voltage doubler
wireless power transfer
Analysis of common-mode interference and jitter of clock receiver circuits with improved topology
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:
Yang X.
;
Zhu Y.
;
Chan C.-H.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:17/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2019/02/11
Isf
Low Clock Jitter Circuit
Self-bias
A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT
Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems, Florence, ITALY, MAY 27-30, 2018
Authors:
Mao F.
;
Lu Y.
;
Lin J.
;
Zhan C.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:14/0
|
TC[WOS]:
0
TC[Scopus]:
3
|
Submit date:2019/02/11
Ac-dc Converter
Current Sensing
Current-mode Active Rectifier
Wireless Charging
Wireless Power Transfer (Wpt)
Quick and cost-efficient A/D converter static characterization using low-precision testing signal
Journal article
MICROELECTRONICS JOURNAL, 2018,Volume: 74,Page: 86-93
Authors:
Qin, Wei Wei
;
Sin, Sai-Weng
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:31/0
|
TC[WOS]:
0
TC[Scopus]:
1
|
Submit date:2018/10/30
Analog-to-digital Converter (Adc)
Static Characterization Estimation
Adc Testing
Ramp Testing
Nonlinear Input Signal
Attenuated Input Signal
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:
Chan, Chi-Hang
;
Zhu, Yan
;
Zhang, Wai-Hong
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:55/0
|
TC[WOS]:
11
TC[Scopus]:
15
|
Submit date:2018/10/30
1-then-2 B/cycle Sar Adc
Analog-to-digital Conversion
Background Offset Calibration
Multi-bit/cycle Sar Adc
Time Interleaving