UM

Browse/Search Results:  1-10 of 29 Help

Selected(0)Clear Items/Page:    Sort:
A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019,Volume: 66,Issue: 1,Page: 116-120
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite  |  View/Download:4/0  |  Submit date:2019/01/17
I/O buffer  mixed-voltage tolerant  PVT variation  leakage  slew rate compensation  
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, NOV 06-08, 2017
Authors:  Chio, U-Fat;  Sin S.-W.;  Seng-Pan U.;  Maloberti F.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Binary-search Adc  Asynchronous  Charge-steering  
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 11,Page: 3166-3174
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite  |  View/Download:3/0  |  Submit date:2018/10/30
Dynamic leakage reduction  I/O buffer  mixed-voltage tolerant  process-voltage-temperature (PVT) variation  slew rate compensation  
Mixed signal controller Patent
专利类型: 发明专利, 专利号: US20170141571A1, 申请日期: 2016-07-24,
Authors:  Man Chung WONG;  Chi Seng LAM;  Yan Zheng YANG;  Wai Hei CHOI;  Ning Yi DAI;  Yajie WU;  Chi Kong WONG;  Sai Weng SIN;  U Fat CHIO;  Seng Pan U;  Rui Paulo da Silva MARTINS
Favorite  |  View/Download:3/0  |  Submit date:2019/03/30
An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Dante Gabriel Muratore;  Alper Akdikmen;  Edoardo Bonizzoni;  Franco Maloberti;  U-Fat Chio;  Sai-Weng Sin;  Rui Paulo Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
Self-Reconfiguration Property of a Mixed Signal Controller for Improving Power Quality Compensation During Light Loading Journal article
IEEE Transactions on Power Electronics, 2015,Volume: 30,Issue: 10,Page: 5938-5951
Authors:  Man-Chung Wong;  Yan-Zheng Yang;  Chi-Seng Lam;  Wai-Hei Choi;  Ning Yi Dai;  Yajie Wu;  Chi-Kong Wong;  Sai-Weng Sin;  U-Fat Chio;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/12/23
Converters  Power Conditioning  Power Quality  Power System Harmonics  Reactive Power  
Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014,Volume: 22,Issue: 2,Page: 372-383
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:7/0  |  Submit date:2018/10/30
Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching  
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2013,Volume: 48,Issue: 8,Page: 1783-1794
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc  
Cascade Analog to Digital Converting System Patent
专利类型: 发明专利, 专利号: US8466823B2, 申请日期: 2011-08-05, 公开日期: 2013-06-18
Authors:  U-Fat CHIO;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite  |  View/Download:7/0  |  Submit date:2019/03/06
Delay generator Patent
专利类型: 发明专利, 专利号: US8441295B2, 申请日期: 2011-11-04,
Authors:  He-Gong Wei;  U-Fat CHIO;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/26