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Histogram-based ratio mismatch calibration for bridge-DAC in 12-bit 120 MS/s SAR ADC Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 3,Page: 1203-1207
Authors:  Yan Zhu;  Chi-Hang Chan;  Si-Seng Wong;  U Seng-Pan;  Rui Paulo Martins
Favorite | View/Download:13/0 | TC[WOS]:10 TC[Scopus]:17 | Submit date:2019/02/11
Bridge Dac  Linearity Calibration  Sar Adc  
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2013,Volume: 48,Issue: 8,Page: 1783-1794
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite | View/Download:23/0 | TC[WOS]:22 TC[Scopus]:30 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc  
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC Conference paper
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, USA, 9-12 Sept. 2012
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | View/Download:21/0 | TC[WOS]:1 TC[Scopus]:7 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Time-interleaved  Sar Adc  Two-step Adc