UM

Browse/Search Results:  1-10 of 22 Help

Selected(0)Clear Items/Page:    Sort:
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC Conference paper
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venezia Lido, ITALY, 22-26 Sept. 2014
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, Singapore, 11-13 Nov. 2013
Authors:  Li Ding;  Wenlan Wu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW Conference paper
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, PEOPLES R CHINA, MAY 19-23, 2013
Authors:  Yun Du;  Tao He;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
A background gain-calibration technique for low voltage pipelined ADCs based on nonlinear interpolation Conference paper
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, 4-7 Aug. 2013
Authors:  Li Ding;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
Digital Calibration  Lms Algorithm  Nonlinear Interpolation  Pipelined Adcs  
A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, SINGAPORE, NOV 11-13, 2013
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure Conference paper
2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 13-15 June 2012
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, DEC 02-05, 2012
Authors:  Yun Du;  Tao He;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, 2-5 Dec. 2012
Authors:  Tao He;  Yun Du;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC Conference paper
Proc. IEEE International Symposium on Circuits and Systems – LASCAS 2010, Iguaçu Falls, Brazil, February 2010
Authors:  Li Ding;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:1/0  |  Submit date:2019/03/28
Digital Offset Calibration  Noise Averaging  Time Interleaved Adc