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A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization
Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:
Wang,Wei
;
Chan,Chi Hang
;
Zhu,Yan
;
Martins,Rui P.
Favorite
|
View/Download:70/0
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2020/12/04
Analog-to-digital conversion (ADC)
continuous-time delta-sigma modulator (CT-DSM)
preliminary sampling and quantization (PSQ) technique
single amplifier biquad (SAB)
successiveapproximation-register (SAR) architecture-based quantizer (QTZ)
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS
Journal article
IEEE Journal of Solid-State Circuits, 2019,Page: 1 - 12
Authors:
Shiheng Yang
;
Jun Yin
;
Haidong Yi
;
Wei-Han Yu
;
Pui-In Mak
;
Rui P. Martins
Favorite
|
View/Download:46/0
|
TC[WOS]:
0
TC[Scopus]:
7
|
Submit date:2019/03/12
Bluetooth Low Energy (Ble)
Cmos
Energy Harvesting
Master-slave Sampling Filter (Mssf)
Micropower Manager (Μpm)
Phase-locked Loop (Pll)
Power Amplifier (Pa)
Power Gating
Transmitter (Tx)
Ultralow-voltage (Ulv)
Voltage-controlled Oscillator (Vco)
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs
Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:
Yang S.
;
Yin J.
;
Mak P.-I.
;
Martins R.P.
Favorite
|
View/Download:31/0
|
TC[WOS]:
3
TC[Scopus]:
6
|
Submit date:2019/02/11
Clock Multiplier
Digital-controlled Delay Line (Dcdl)
Frequency-tracking Loop (Ftl)
Injection-locked Phase-locked Loop (Il-pll)
Multiplying Delay-locked Loop (Mdll)
Phase Noise
Ring Voltage-controlled Oscillator (Rvco)
Root-mean-square (Rms) Jitter
Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 12,Page: 3455-3469
Authors:
Jiang, Yang
;
Law, Man-Kay
;
Mak, Pui-In
;
Martins, Rui P.
Favorite
|
View/Download:18/0
|
TC[WOS]:
1
TC[Scopus]:
4
|
Submit date:2019/01/17
Algorithmic voltage-feed-in (AVFI) topology
buck-boost
dc-dc
linear topology
parasitic loss
power density
rational voltage conversion ratio
reconfigurable
reference-selective bootstrapping
switched capacitor
An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 12,Page: 3528-3539
Authors:
Lim, Chee Cheow
;
Ramiah, Harikrishnan
;
Yin, Jun
;
Mak, Pui-In
;
Martins, Rui P.
Favorite
|
View/Download:10/0
|
TC[WOS]:
1
TC[Scopus]:
8
|
Submit date:2019/01/17
Figure of merit (FoM)
flicker noise upcon-version
inverse-class-F (class-F-1) oscillator
phase noise (PN)
second harmonic resonance
voltage-biased oscillator
An Inverse-Class-F CMOS Oscillator with Intrinsic-High-Q 1st-Harmonic and 2nd-Harmonic Resonances
Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 12,Page: 3528 - 3539
Authors:
Chee Cheow Lim
;
Harikrishnan Ramiah
;
Jun Yin
;
Pui-In Mak
;
Rui P. Martins
Favorite
|
View/Download:31/0
|
TC[WOS]:
1
TC[Scopus]:
8
|
Submit date:2019/03/12
Figure Of Merit (Fom)
Flicker Noise Upconversion
Inverse-class-f (Class-f−1) Oscillator
Phase Noise (Pn)
Second Harmonic Resonance
Voltage-biased Oscillator
An inverse-class-F CMOS oscillator with intrinsic-high-Q first harmonic and second harmonic resonances
Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 12,Page: 3528-3539
Authors:
Lim C.C.
;
Ramiah H.
;
Yin J.
;
Mak P.-I.
;
Martins R.P.
Favorite
|
View/Download:8/0
|
TC[WOS]:
1
TC[Scopus]:
8
|
Submit date:2019/02/11
Figure of merit (FoM)
flicker noise upconversion
inverse-class-F (class-F-1) oscillator
phase noise (PN)
second harmonic resonance
voltage-biased oscillator
Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 11,Page: 3232-3242
Authors:
Peng, Yatao
;
Yin, Jun
;
Mak, Pui-In
;
Martins, Rui P.
Favorite
|
View/Download:39/0
|
TC[WOS]:
3
TC[Scopus]:
8
|
Submit date:2019/01/17
Frequency-tuning range (FTR)
LC tank
millimeter-wave (mm-wave)
mode switching
multi-mode resonance
phase noise (PN)
switched inductor
voltage-controlled oscillator (VCO)
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS
Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 10,Page: 2783-2794
Authors:
Wang,Wei
;
Zhu,Yan
;
Chan,Chi Hang
;
Martins,Rui Paulo
Favorite
|
View/Download:9/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2019/08/22
Analog-to-digital conversion (ADC)
continuous-time (CT) delta-sigma modulator
DAC driver
passive integrator
single amplifier biquad (SAB)
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS
Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 10,Page: 2783-2794
Authors:
Wang W.
;
Zhu Y.
;
Chan C.-H.
;
Martins R.P.
Favorite
|
View/Download:10/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2019/02/11
Analog-to-digital conversion (ADC)
continuous-time (CT) delta-sigma modulator
DAC driver
passive integrator
single amplifier biquad (SAB)