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An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac Journal article
IEEE Journal of Solid-State Circuits, 2012,Volume: 47,Issue: 11,Page: 2763-2772
Authors:  Hegong Wei;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite | View/Download:13/0 | TC[WOS]:51 TC[Scopus]:0 | Submit date:2018/10/30
2-b-per-cycle (2 B/c)  Analog-to-digital Converter (Adc)  Resistive Dac  Successive Approximation Register (Sar)  
A 0.024mm28b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Wei, Hegong;  Chan, Chi-Hang;  Chio, U.-Fat;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui;  Maloberti, Franco
Favorite | View/Download:4/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2018/11/06