×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
Title
Creator
Date Issued
Subject Area
Keyword
Document Type
Source Publication
Date Accessioned
Indexed By
Publisher
Funding Project
MOST Discipline Catalogue
Study Hall
Image search
Paste the image URL
Home
Collections
Authors
DocType
Subjects
K-Map
Evaluation
K-Integration
News
Search in the results
Collection
INSTITUTE... [43]
Faculty o... [40]
THE STATE ... [3]
Authors
CHAN CHI ... [41]
ZHU YAN [37]
RUI PAULO... [35]
U SENG PA... [34]
SIN SAI W... [31]
VAI MANG I [1]
More...
Document Type
Journal a... [21]
Conferenc... [19]
Patent [12]
论文 [5]
Date Issued
2020 [2]
2019 [2]
2018 [8]
2017 [13]
2016 [6]
2015 [3]
More...
Language
英语 [53]
Source Publication
IEEE Journ... [8]
IEEE TRANS... [5]
IEEE Trans... [4]
IEEE TRANS... [3]
Digest of ... [2]
IEEE JOURN... [2]
More...
Funding Project
Indexed By
SCI [37]
CPCI [4]
其他 [1]
Funding Organization
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-10 of 57
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Issue Date Ascending
Issue Date Descending
Submit date Ascending
Submit date Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization
Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:
Wang,Wei
;
Chan,Chi Hang
;
Zhu,Yan
;
Martins,Rui P.
Favorite
|
View/Download:70/0
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2020/12/04
Analog-to-digital conversion (ADC)
continuous-time delta-sigma modulator (CT-DSM)
preliminary sampling and quantization (PSQ) technique
single amplifier biquad (SAB)
successiveapproximation-register (SAR) architecture-based quantizer (QTZ)
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp
Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:
Xing,Kai
;
Wang,Wei
;
Zhu,Yan
;
Chan,Chi Hang
;
Martins,Rui Paulo
Favorite
|
View/Download:74/0
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2020/12/04
3-stage opamp
CTSDM
SAB Integrator
20.7 A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ
Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:
Wang,Wei
;
Chan,Chi Hang
;
Zhu,Yan
;
Martins,Rui P.
Favorite
|
View/Download:73/0
|
TC[WOS]:
0
TC[Scopus]:
5
|
Submit date:2020/12/04
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019,Volume: 66,Issue: 1,Page: 82-93
Authors:
Li, Cheng
;
Chan, Chi-Hang
;
Zhu, Yan
;
Martins, Rui P.
Favorite
|
View/Download:22/0
|
TC[WOS]:
1
TC[Scopus]:
3
|
Submit date:2019/01/17
Reference error
reference buffer
successive-approximation-register (SAR)
analog-to-digital converter (ADC)
reference ripple
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC
Conference paper
Authors:
Wang, Guancheng
;
Li, Cheng
;
Zhu, Yan
;
Zhong, Jianyu
;
Lu, Yan
;
Chan, Chi-Hang
;
Martins, Rui P.
Favorite
|
View/Download:49/0
|
TC[WOS]:
0
TC[Scopus]:
2
|
Submit date:2018/10/30
Gain error calibration
testing signal generation
SAR ADC
bridge DAC
low-dropout (LDO) regulator
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS
Conference paper
Authors:
Zhu, Yan
;
Chan, Chi-Hang
;
Zheng, Zi-Hao
;
Li, Cheng
;
Zhong, Jian-Yu
;
Martins, Rui P.
Favorite
|
View/Download:48/0
|
TC[WOS]:
2
TC[Scopus]:
4
|
Submit date:2018/10/30
Time-interleaved ADC
sampling front-end design
passive sharing
pipelined-SAR ADC
switch bootstrap technique
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538
Authors:
Wang, X. Shawn
;
Jin, Xin
;
Du, Jieqiong
;
Li, Yilei
;
Du, Yuan
;
Wong, Chien-Heng
;
Kuan, Yen-Cheng
;
Chan, Chi-Hang
;
Chang, Mau-Chung Frank
Favorite
|
View/Download:10/0
|
TC[WOS]:
3
TC[Scopus]:
3
|
Submit date:2019/01/17
Analog-to-digital converter (ADC)
virtual-ground sampling
SAR
time-interleaved
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 11,Page: 2279-2289
Authors:
Wang, Guan Cheng
;
Zhu, Yan
;
Chan, Chi-Hang
;
Seng-Pan, U.
;
Martins, Rui P.
Favorite
|
View/Download:19/0
|
TC[WOS]:
0
TC[Scopus]:
1
|
Submit date:2019/01/17
Bridge digital-to-analog converter (DAC)
gain error calibration
successive approximation register (SAR)
analog-to-digital converters (ADCs)
testing signal generation (TSG)
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Delta Sigma Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS
Conference paper
Authors:
Wang, Wei
;
Zhu, Yan
;
Chan, Chi-Hang
;
Martins, Rui Paulo
Favorite
|
View/Download:29/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2018/10/30
Terms-Analog-to-digital conversion (ADC)
continuous-time (CT) delta-sigma modulator
DAC driver
passive integrator
single amplifier biquad (SAB)
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS
Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 10,Page: 2783-2794
Authors:
Wang,Wei
;
Zhu,Yan
;
Chan,Chi Hang
;
Martins,Rui Paulo
Favorite
|
View/Download:9/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2019/08/22
Analog-to-digital conversion (ADC)
continuous-time (CT) delta-sigma modulator
DAC driver
passive integrator
single amplifier biquad (SAB)