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Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:19/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
background calibration  current integrating sampler  Time-interleaved ADC  timing skew  
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Authors:  Mao F.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11
delay compensation  feedback loop  implantable medical devices  real time  voltage doubler  wireless power transfer  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:36/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite  |  View/Download:28/0  |  Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
A dual-output SC converter with dynamic power allocation for multicore application processors Conference paper
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Authors:  Jiang J.;  Lu Y.;  Liu X.;  Ki W.-H.;  Mok P.K.T.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:2/0  |  Submit date:2019/02/11
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, November 6-8, 2017
Authors:  Wei Wang;  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U.;  Rui Paulo Martins
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
A Digital PWM Controlled KY Step-Up Converter Based on Frequency Domain ΣΔ ADC Conference paper
IEEE International Symposium on Industrial Electronics, Edinburgh, UK, JUN 18-21, 2017
Authors:  Xia Du;  Chi-Seng Lam;  Sai-Weng Sin;  Man-Kay Law;  Franco Maloberti;  Man-Chung Wong;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:18/0  |  Submit date:2018/12/23
Frequency Domain Sigma-delta Adc  Ky Converter  Digital Control