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Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias  
A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems, Florence, ITALY, MAY 27-30, 2018
Authors:  Mao F.;  Lu Y.;  Lin J.;  Zhan C.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
Ac-dc Converter  Current Sensing  Current-mode Active Rectifier  Wireless Charging  Wireless Power Transfer (Wpt)  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:23/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite  |  View/Download:13/0  |  Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
Passive Noise Shaping in SAR ADC With Improved Efficiency Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 2,Page: 416-420
Authors:  Song, Yan;  Chan, Chi-Hang;  Zhu, Yan;  Geng, Li;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:21/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Delta Sampling  Oversampling  Passive Noise Shaping (Pns)  Successive Approximation Register (Sar)  
An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 1,Page: 20-34
Authors:  Huang M.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
Amplifier  Analog Assisted (Aa)  Coarse/fine Tuning  Digital Control  Fully Integrated Voltage Regulator (Fivr)  Limit Cycle Oscillation (Lco)  Low-dropout (Ldo) Regulator  Nonlinear Control  Output-capacitor-free  Power Management  
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, November 6-8, 2017
Authors:  Wei Wang;  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U.;  Rui Paulo Martins
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression Conference paper
Proceedings IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, PEOPLES R CHINA, OCT 29-NOV 01, 2017
Authors:  Chi-Wa U.;  Lam C.-S.;  Law M.-K.;  Sin S.-W.;  Wong M.-C.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:7/0  |  Submit date:2018/12/23
Continuous-conduction Mode (Ccm)  Luo Converter  Parameter Design  Voltage Ripple  
A missing-code-detection gain error calibration achieving 63dB SNR for An 11-bit ADC Conference paper
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, BELGIUM, SEP 11-14, 2017
Authors:  Wang G.-C.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:16/0  |  Submit date:2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator