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Analysis of common-mode interference and jitter of clock receiver circuits with improved topology
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:
Yang X.
;
Zhu Y.
;
Chan C.-H.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:17/0
|
TC[WOS]:
3
TC[Scopus]:
5
|
Submit date:2019/02/11
Isf
Low Clock Jitter Circuit
Self-bias
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:
Chan, Chi-Hang
;
Zhu, Yan
;
Zhang, Wai-Hong
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:55/0
|
TC[WOS]:
11
TC[Scopus]:
15
|
Submit date:2018/10/30
1-then-2 B/cycle Sar Adc
Analog-to-digital Conversion
Background Offset Calibration
Multi-bit/cycle Sar Adc
Time Interleaving
Passive Noise Shaping in SAR ADC With Improved Efficiency
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 2,Page: 416-420
Authors:
Song, Yan
;
Chan, Chi-Hang
;
Zhu, Yan
;
Geng, Li
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:41/0
|
TC[WOS]:
3
TC[Scopus]:
7
|
Submit date:2018/10/30
Analog-to-digital Converter (Adc)
Delta Sampling
Oversampling
Passive Noise Shaping (Pns)
Successive Approximation Register (Sar)
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS
Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, November 6-8, 2017
Authors:
Wei Wang
;
Yan Zhu
;
Chi-Hang Chan
;
Seng-Pan U.
;
Rui Paulo Martins
Favorite
|
View/Download:24/0
|
TC[WOS]:
0
TC[Scopus]:
3
|
Submit date:2019/02/11
A missing-code-detection gain error calibration achieving 63dB SNR for An 11-bit ADC
Conference paper
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, BELGIUM, SEP 11-14, 2017
Authors:
Wang G.-C.
;
Zhu Y.
;
Chan C.-H.
;
Seng-Pan U.
;
Martins R.P.
Favorite
|
View/Download:28/0
|
TC[WOS]:
2
TC[Scopus]:
2
|
Submit date:2019/02/11
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration
Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:
Chan, Chi-Hang
;
Zhu, Yan
;
Li, Cheng
;
Zhang, Wai-Hong
;
Ho, Iok-Meng
;
Wei, Lai
;
Seng-Pan, U.
;
Martins, Rui Paulo
Favorite
|
View/Download:36/0
|
TC[WOS]:
12
TC[Scopus]:
19
|
Submit date:2018/10/30
Reference Buffer
Reference Error Calibration
Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)
Threshold Reconfigurable Comparator
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:
Chan, Chi-Hang
;
Zhu, Yan
;
Sin, Sai-Weng
;
Seng-Pan, U.
;
Martins, Rui P.
;
Maloberti, Franco
Favorite
|
View/Download:45/0
|
TC[WOS]:
5
TC[Scopus]:
8
|
Submit date:2018/10/30
Analog-to-digital Converter (Adc)
Flash
Time-based Dual-edge-triggered
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC
Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:
Jianyu Zhong
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:27/0
|
TC[WOS]:
9
TC[Scopus]:
11
|
Submit date:2019/02/11
Analog-to-digital Converter (Adc)
Low Power
Successive Approximation Architecture
Switched-capacitor Circuits
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration
Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:
Chi-Hang Chan
;
Yan Zhu
;
Iok-Meng Ho
;
Wai-Hong Zhang
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:23/0
|
TC[WOS]:
18
TC[Scopus]:
24
|
Submit date:2018/11/06
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching
Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:
Dezhi Xing
;
Yan Zhu
;
Chi-Hang Chan
;
Sai-Weng Sin
;
Fan Ye
;
Junyan Ren
;
Seng-Pan U
;
Rui Paulo Martins
Favorite
|
View/Download:33/0
|
TC[WOS]:
5
TC[Scopus]:
8
|
Submit date:2019/02/11
Common Mode Variation
Partial Vcm-based Switching
Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)