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A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Guohe Yin;  He-Gong Wei;  U–Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
Analgo-to-digital Converter  Successive Approximation Register  Ultra-low Power  Sensor Applications  
A 22.4 μw 80dB SNDR ΣΔ modulator with passive analog adder and SAR quantizer for EMG application Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors:  Zhijie Chen;  Yang Jiang;  Chenyan Cai;  He-Gong Wei;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Σδ Modulator  Sar Quantizer  Passive Analog Adder  
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US20120229313A1, 申请日期: 2011-09-14,
Authors:  Sai-Weng SIN;  He-Gong WEI;  Franco MALOBERTI;  Li DING;  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Seng-Pan U;  Rui Paulo da Silva MARTINS
Favorite  |  View/Download:4/0  |  Submit date:2019/02/26