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| A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, Singapore, 11-13 Nov. 2013
Authors: Li Ding; Wenlan Wu; Sai-Weng Sin ; Seng-Pan U; R.P.Martins
  Favorite | View/Download：17/0 | TC[WOS]:3 TC[Scopus]:3 | Submit date：2019/02/11 |
| A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW Conference paper
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, PEOPLES R CHINA, MAY 19-23, 2013
Authors: Yun Du; Tao He; Yang Jiang; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：21/0 | TC[WOS]:0 TC[Scopus]:2 | Submit date：2019/02/11 |
| A background gain-calibration technique for low voltage pipelined ADCs based on nonlinear interpolation Conference paper
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, 4-7 Aug. 2013
Authors: Li Ding; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：13/0 | TC[WOS]:0 TC[Scopus]:1 | Submit date：2019/02/11
Digital Calibration Lms Algorithm Nonlinear Interpolation Pipelined Adcs |
| A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure Conference paper
2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 13-15 June 2012
Authors: Chi-Hang Chan; Yan Zhu; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：16/0 | TC[WOS]:0 TC[Scopus]:41 | Submit date：2019/02/11 |
| A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors: Yan Zhu; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：25/0 | TC[WOS]:0 TC[Scopus]:29 | Submit date：2019/02/11 |
| A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, DEC 02-05, 2012
Authors: Yun Du; Tao He; Yang Jiang; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：13/0 | TC[WOS]:2 TC[Scopus]:2 | Submit date：2019/02/11 |
| A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, 2-5 Dec. 2012
Authors: Tao He; Yun Du; Yang Jiang; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：10/0 | TC[WOS]:2 TC[Scopus]:2 | Submit date：2019/02/11 |
| A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS Journal article
澳門機電工程專業協會(APEMEM)會刊, 2009
Authors: Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：10/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/28
Index Terms-pipelined Adc Low-voltage Current-mode Comparator |
| Linearity analysis on a series-split capacitor array for high-speed SAR ADCs Conference paper
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, Knoxville, TN, AUG 10-13, 2008
Authors: Yan Zhu; U-Fat Chio; He-Gong Wei; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：27/0 | TC[WOS]:7 TC[Scopus]:16 | Submit date：2019/02/11 |
| A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feed Forward Technique Conference paper
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), Macao, PEOPLES R CHINA, NOV 30-DEC 03, 2008
Authors: Li Ding; Sio Chan; Kim-Fai Wong; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | View/Download：9/0 | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/03/06 |
