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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure Conference paper
2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 13-15 June 2012
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite | View/Download:16/0 | TC[WOS]:0 TC[Scopus]:41 | Submit date:2019/02/11
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite | View/Download:25/0 | TC[WOS]:0 TC[Scopus]:29 | Submit date:2019/02/11
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, DEC 02-05, 2012
Authors:  Yun Du;  Tao He;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite | View/Download:13/0 | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/11
A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity Conference paper
2012 IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, TAIWAN, 2-5 Dec. 2012
Authors:  Tao He;  Yun Du;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite | View/Download:10/0 | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/11