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A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:19/0  |  Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:20/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
A 0.044-mm2 0.5-To-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 1,Page: 71-75
Authors:  Yu H.;  Chen Y.;  Boon C.C.;  Li C.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:23/0  |  Submit date:2019/02/11
Cmos  Low-noise Amplifier (Lna)  Noise Cancelling  Noise Figure (Nf)  Resistor Feedback  Source Follower Feedback (Sff)  Wideband Input Impedance Matching  
A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 237-241
Authors:  Lim C.C.;  Ramiah H.;  Yin J.;  Kumar N.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:15/0  |  Submit date:2019/02/14
Class-c  Cmos  Current-reuse  Mode Switching  Phase Noise (Pn)  Single-ended Complementary (Sec)  Voltage-controlled Oscillator (Vco)  Wideband  
Many-objective sizing optimization of a class-C/D VCO for ultralow-power iot and ultralow-phase-noise cellular applications Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 1,Page: 69-82
Authors:  Martins R.;  Lourenco N.;  Horta N.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
Dual-mode Voltage-controlled Oscillator (Voc)  Electronic Design Automation (Eda)  Many-objective Optimization  Multitest Bench Sizing Optimization  Radio Frequency (Rf) Integrated Circuits (Ics)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:25/0  |  Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Xu K.;  Yin J.;  Mak P.-I.;  Staszewski R.B.;  Martins R.P.
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
background calibration  current integrating sampler  Time-interleaved ADC  timing skew  
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11