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A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, USA, 18-22 June 2018
Authors:  Song Y.;  Zhu Y.;  Chan C.-H.;  Geng L.;  Martins R.P.
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Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
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Isf  Low Clock Jitter Circuit  Self-bias  
A missing-code-detection gain error calibration achieving 63dB SNR for An 11-bit ADC Conference paper
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, BELGIUM, SEP 11-14, 2017
Authors:  Wang G.-C.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
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A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration Conference paper
2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, 12-16 Sept. 2011
Authors:  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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A time-efficient dither-injection scheme for pipelined SAR ADC Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Wang R.;  Chio U.-F.;  Chan C.-H.;  Ding L.;  Sin S.-W.;  Seng-Pan U.;  Wang Z.;  Martins R.P.
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Digital Calibration  Dither Injection  Pipelined  Sar Adc  
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS Conference paper
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, Jeju, South Korea, 14-16 Nov. 2011
Authors:  Chan C.-H.;  Zhu Y.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators Conference paper
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, Jeju, South Korea, 14-16 Nov. 2011
Authors:  Wong S.-S.;  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc  Flash Adc  Sar Adc  
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation Conference paper
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, Jeju, SOUTH KOREA, NOV 14-16, 2011
Authors:  Zhu Y.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.;  Maloberti F.
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An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H Conference paper
2010 Proceedings of ESSCIRC, Seville, Spain, 14-16 Sept. 2010
Authors:  Sin S.-W.;  Ding L.;  Zhu Y.;  Wei H.-G.;  Chan C.-H.;  Chio U.-F.;  Seng-Pan U.;  Martins R.P.;  Maloberti F.
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A power effective 5-bit 600 MS/s binary-search ADC with simplified switching Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Wong S.S.;  Chio U.-F.;  Choi H.-L.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc