UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-10 of 95 Help

Filters        
Selected(0)Clear Items/Page:    Sort:
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:20/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
background calibration  current integrating sampler  Time-interleaved ADC  timing skew  
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Authors:  Mao F.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11
delay compensation  feedback loop  implantable medical devices  real time  voltage doubler  wireless power transfer  
A dual-output SC converter with dynamic power allocation for multicore application processors Conference paper
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Authors:  Jiang J.;  Lu Y.;  Liu X.;  Ki W.-H.;  Mok P.K.T.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
Capacitive Floating Level Shifter: Modeling and Design Conference paper
TENCON 2015 - 2015 IEEE Region 10 Conference, Macao, China, 1-4 Nov. 2015
Authors:  Wen-Ming Zheng;  Chi-Seng Lam;  Sai-Weng Sin;  Yan Lu;  Man-Chung Wong;  Seng-Pan U.;  R.P. Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/12/23
Level Shifter  Floating Level Shifter  Dc-dc Converter  Fully-integrated  Switched-capacitor  
A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer Conference paper
ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems, Seoul, South Korea, 20-23 May 2012
Authors:  He T.;  Jiang Y.;  Du Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration Conference paper
2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, 12-16 Sept. 2011
Authors:  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
A time-efficient dither-injection scheme for pipelined SAR ADC Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Wang R.;  Chio U.-F.;  Chan C.-H.;  Ding L.;  Sin S.-W.;  Seng-Pan U.;  Wang Z.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Digital Calibration  Dither Injection  Pipelined  Sar Adc