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A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:19/0  |  Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 0.044-mm2 0.5-To-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 1,Page: 71-75
Authors:  Yu H.;  Chen Y.;  Boon C.C.;  Li C.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:23/0  |  Submit date:2019/02/11
Cmos  Low-noise Amplifier (Lna)  Noise Cancelling  Noise Figure (Nf)  Resistor Feedback  Source Follower Feedback (Sff)  Wideband Input Impedance Matching  
A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 237-241
Authors:  Lim C.C.;  Ramiah H.;  Yin J.;  Kumar N.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:15/0  |  Submit date:2019/02/14
Class-c  Cmos  Current-reuse  Mode Switching  Phase Noise (Pn)  Single-ended Complementary (Sec)  Voltage-controlled Oscillator (Vco)  Wideband  
Many-objective sizing optimization of a class-C/D VCO for ultralow-power iot and ultralow-phase-noise cellular applications Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 1,Page: 69-82
Authors:  Martins R.;  Lourenco N.;  Horta N.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
Dual-mode Voltage-controlled Oscillator (Voc)  Electronic Design Automation (Eda)  Many-objective Optimization  Multitest Bench Sizing Optimization  Radio Frequency (Rf) Integrated Circuits (Ics)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:25/0  |  Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Xu K.;  Yin J.;  Mak P.-I.;  Staszewski R.B.;  Martins R.P.
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 10,Page: 3196-3206
Authors:  Kong L.;  Chen Y.;  Boon C.C.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Automatic Gain Control (Agc) Amplifier  Bipolar Junction Transistors (Bjts)  Cmos  Db-linear  Dynamic Range  Negative Exponential Generator (Neg)  Pseudo-exponential Function  Rational Approximation  Taylor Series  
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 3014-3026
Authors:  Chen Y.;  Mak P.-I.;  Boon C.C.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 2889-2902
Authors:  Cheang C.-F.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
Carrier-aggregation  Digital Predistortion (Dpd)  Field-programmable Gate Array (Fpga)  Identification  Power Amplifier (Pa)  Recursive Least Square (Rls)  
A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter with 34.7% Peak System Efficiency Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 9,Page: 1174-1178
Authors:  Peng X.;  Yin J.;  Yu W.-H.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Battery Capacity Usage (Bcu)  Bluetooth Low-energy (Ble)  Cmos  Direct-coin-battery-powered (Dcbp)  Output Power  Power Amplifier (Pa)  System Efficiency