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An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Chio U.-F.;  Wen K.-C.;  Sin S.-W.;  Lam C.-S.;  Lu Y.;  Maloberti F.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
fully integrated  SC DC-DC converter  switched-capacitor  voltage-controlled oscillator (VCO)  
An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Zhu Y.;  Chan C.-H.;  Martins R.P.
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A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Xu K.;  Yin J.;  Mak P.-I.;  Staszewski R.B.;  Martins R.P.
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A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
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background calibration  current integrating sampler  Time-interleaved ADC  timing skew  
An inverse-class-F CMOS oscillator with intrinsic-high-Q first harmonic and second harmonic resonances Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 12,Page: 3528-3539
Authors:  Lim C.C.;  Ramiah H.;  Yin J.;  Mak P.-I.;  Martins R.P.
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Figure of merit (FoM)  flicker noise upconversion  inverse-class-F (class-F-1) oscillator  phase noise (PN)  second harmonic resonance  voltage-biased oscillator  
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3707-3719
Authors:  Wang G.;  Li C.;  Zhu Y.;  Zhong J.;  Lu Y.;  Chan C.-H.;  Martins R.P.
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bridge DAC  Gain error calibration  low-dropout (LDO) regulator  SAR ADC  testing signal generation  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
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passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
Nano-ampere low-dropout regulator designs for IoT devices Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 4017-4026
Authors:  Huang Y.;  Lu Y.;  Maloberti F.;  Martins R.P.
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dynamic current boosting  LDO regulator  output-capacitor-free LDO regulator  ultra-low quiescent LDO  
A 220-MHz bondwire-based fully-integrated ky converter with fast transient response under DCM Operation Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3984-3995
Authors:  Zeng W.-L.;  Lam C.-S.;  Sin S.-W.;  Maloberti F.;  Wong M.-C.;  Martins R.P.
Favorite  |  View/Download:10/0  |  Submit date:2018/12/23
Bondwire Inductor  Boost Converter  Discontinuous Conduction Mode (Dcm)  Fully Integrated Ky Converter  Load Transient Response  Pwm  Voltage Ripple  Zero Current Detection (Zcd)  
A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, USA, 18-22 June 2018
Authors:  Song Y.;  Zhu Y.;  Chan C.-H.;  Geng L.;  Martins R.P.
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