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Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 1,Page: 82-93
Authors:  Li C.;  Chan C.-H.;  Zhu Y.;  Martins R.P.
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
analog-to-digital converter (ADC)  reference buffer  Reference error  reference ripple  successive-approximation-register (SAR)  
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3707-3719
Authors:  Wang G.;  Li C.;  Zhu Y.;  Zhong J.;  Lu Y.;  Chan C.-H.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
bridge DAC  Gain error calibration  low-dropout (LDO) regulator  SAR ADC  testing signal generation  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
Nano-ampere low-dropout regulator designs for IoT devices Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 4017-4026
Authors:  Huang Y.;  Lu Y.;  Maloberti F.;  Martins R.P.
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
dynamic current boosting  LDO regulator  output-capacitor-free LDO regulator  ultra-low quiescent LDO  
A 220-MHz bondwire-based fully-integrated ky converter with fast transient response under DCM Operation Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3984-3995
Authors:  Zeng W.-L.;  Lam C.-S.;  Sin S.-W.;  Maloberti F.;  Wong M.-C.;  Martins R.P.
Favorite  |  View/Download:10/0  |  Submit date:2018/12/23
Bondwire Inductor  Boost Converter  Discontinuous Conduction Mode (Dcm)  Fully Integrated Ky Converter  Load Transient Response  Pwm  Voltage Ripple  Zero Current Detection (Zcd)  
A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 10,Page: 3196-3206
Authors:  Kong L.;  Chen Y.;  Boon C.C.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Automatic Gain Control (Agc) Amplifier  Bipolar Junction Transistors (Bjts)  Cmos  Db-linear  Dynamic Range  Negative Exponential Generator (Neg)  Pseudo-exponential Function  Rational Approximation  Taylor Series  
A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 3014-3026
Authors:  Chen Y.;  Mak P.-I.;  Boon C.C.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 9,Page: 2889-2902
Authors:  Cheang C.-F.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
Carrier-aggregation  Digital Predistortion (Dpd)  Field-programmable Gate Array (Fpga)  Identification  Power Amplifier (Pa)  Recursive Least Square (Rls)  
Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias