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A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite  |  View/Download:19/0  |  Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
Drug screening of cancer cell lines and human primary tumors using droplet microfluidics Journal article
SCIENTIFIC REPORTS, 2017,Volume: 7,Page: 9109
Authors:  Wong, Ada Hang-Heng;  Li, Haoran;  Jia, Yanwei;  Mak, Pui-In;  da Silva Martins, Rui Paulo;  Liu, Yan;  Vong, Chi Man;  Wong, Hang Cheong;  Wong, Pak Kin;  Wang, Haitao;  Sun, Heng;  Deng, Chu-Xia
Favorite  |  View/Download:13/0  |  Submit date:2018/10/30
High-/mixed-voltage analog and RF circuit techniques for nanoscale CMOS Book
UNITED STATES:High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS, 2012
Authors:  Mak, Pui-In;  Martins, Rui Paulo
Favorite  |  View/Download:6/0  |  Submit date:2018/11/06
Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering Book
US:Springer US, 2006
Authors:  U Seng Pan;  Martins Rui Paulo;  Epifanio da Franca Jose de Albuquerque
Favorite  |  View/Download:6/0  |  Submit date:2019/02/26
Cmos  Cmos Analog Integrated Circuit  Filter  Front-end Filtering  Gain & Offset Compensation  High-frequency  Multirate Signal Processing  Secs  Switched-capacitor  The Kluwer International Series In engIneerIng And Computer  Timing-mismatch And Jitter  Calculus  Consumption  Integrated Circuit