UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-10 of 31 Help

Filters        
Selected(0)Clear Items/Page:    Sort:
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:32/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017,Volume: 64,Issue: 7,Page: 1684-1695
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:21/0  |  Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)  
Metastablility in SAR ADCs Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Boris Murmann;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Comparator  Metastability  Successive Approximation Register (Sar)  
Active-Passive Delta Sigma Modulator for High-Resolution and Low-Power Applications Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 364-374
Authors:  Hussain, Arshad;  Sin, Sai-Weng;  Chan, Chi-Hang;  U, Seng-Pan (Ben);  Maloberti, Franco;  Martins, Rui P.
Favorite  |  View/Download:23/0  |  Submit date:2018/10/30
Delta-Sigma Modulator (Delta Sigma m)  Discrete Time (Dt)  Low-gain-amplifier-based Switched-capacitor (Sc) Integrator  Noise Shaping  Passive Sc Integrator  
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS Journal article
Journal of Semiconductor Technology and Science, 2016,Volume: 16,Issue: 4,Page: 395-404
Authors:  Jianwei Liu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
4x Time-domain Interpolation  Flash Adc  Sr-latch  Time Comparator  
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 7,Page: 2603-2607
Authors:  Jianwei Liu;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite  |  View/Download:19/0  |  Submit date:2019/02/14
Background Linearity Calibration  Splitdigital- To-analog Converter (Dac)  Successive Approximation Register (Sar) Adc  Uniform Quantization Theory (Uqt)  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS Conference paper
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, United states, 22-26 Feb. 2015
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:12/0  |  Submit date:2018/11/06