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A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:31/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
Metastablility in SAR ADCs Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Boris Murmann;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Comparator  Metastability  Successive Approximation Register (Sar)  
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS Journal article
Electronics Letters, 2016,Volume: 52,Issue: 16,Page: 1368-1370
Authors:  Yan Lu;  Cheng Li;  Yan Zhu;  Mo Huang;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS Conference paper
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, United states, 22-26 Feb. 2015
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:11/0  |  Submit date:2018/11/06
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC Conference paper
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, USA, 9-12 Sept. 2012
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Time-interleaved  Sar Adc  Two-step Adc  
Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
Design and experimental verification of a power effective Flash-SAR subranging ADC Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010,Volume: 57,Issue: 8,Page: 607-611
Authors:  U-Fat Chio;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins;  Franco Maloberti
Favorite  |  View/Download:24/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Digital Error Correction (Dec)  Flash Adc  Sar Adc  Subranging Adc  
A rapid power-switchable track-and-hold amplifier in 90-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010,Volume: 57,Issue: 1,Page: 16
Authors:  He-Gong Wei;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:14/0  |  Submit date:2018/10/30
High-accuracy  High-speed  Power Switchable  Track-and-hold (T/h)