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A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:31/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:20/0  |  Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)  
Metastablility in SAR ADCs Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Boris Murmann;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Comparator  Metastability  Successive Approximation Register (Sar)  
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014,Volume: 22,Issue: 2,Page: 372-383
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:11/0  |  Submit date:2018/10/30
Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching  
A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2013,Volume: 48,Issue: 9,Page: 2154-2169
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:12/0  |  Submit date:2018/10/30
Analog-to-digital Conversion (Adc)  Calibration  Embedded Reference  Flash Adc  Folding  Low Power  
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation Journal article
IEEE Journal of Solid-State Circuits, 2012,Volume: 47,Issue: 11,Page: 2614-2626
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:13/0  |  Submit date:2018/10/30
Decoupled Flip-around Mdac  Offset-cancellation  Pipelined-sar Adc  Vdd -attenuator  
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2010,Volume: 45,Issue: 6,Page: 1111-1121
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:94/0  |  Submit date:2018/10/30
Charge-recovery  Reference-free  Switched Technique