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A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, November 6-8, 2017
Authors:  Wei Wang;  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U.;  Rui Paulo Martins
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 5-9 Feb. 2017
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/11/06
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS Conference paper
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, United states, 22-26 Feb. 2015
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:11/0  |  Submit date:2018/11/06
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC Conference paper
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venezia Lido, ITALY, 22-26 Sept. 2014
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS Conference paper
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, SINGAPORE, NOV 11-13, 2013
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS Conference paper
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, PEOPLES R CHINA, MAY 19-23, 2013
Authors:  Wen-Lan Wu;  Yan Zhu;  Li Ding;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:12/0  |  Submit date:2019/02/11
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure Conference paper
2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 13-15 June 2012
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11