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An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Kuala Lumpur, MALAYSIA, DEC 06-09, 2010
Authors:  Li D.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | View/Download:6/0 | TC[WOS]:2 TC[Scopus]:0 | Submit date:2019/02/11
Capacitor Mismatch  Digital Calibration  Interstage Gain Error  Pipelined Adcs  
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Kuala Lumpur, MALAYSIA, DEC 06-09, 2010
Authors:  Jiang Y.;  Wong K.-F.;  Cai C.-Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite | View/Download:10/0 | TC[WOS]:2 TC[Scopus]:0 | Submit date:2019/02/11
Clock-jitter Sensitivity  Continuous-time  Sigma-delta Modulator  Switched Current Dac  
A Process- and temperature- insensitive current-controlled delay generator for sampled-data systems Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Macao, PEOPLES R CHINA, NOV 30-DEC 03, 2008
Authors:  Wei H.-G.;  Chio U.-F.;  Zhu Y.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | View/Download:11/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11