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A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | View/Download:46/0 | TC[WOS]:11 TC[Scopus]:0 | Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
Passive Noise Shaping in SAR ADC With Improved Efficiency Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 2,Page: 416-420
Authors:  Song, Yan;  Chan, Chi-Hang;  Zhu, Yan;  Geng, Li;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | View/Download:33/0 | TC[WOS]:3 TC[Scopus]:0 | Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Delta Sampling  Oversampling  Passive Noise Shaping (Pns)  Successive Approximation Register (Sar)  
An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac Journal article
IEEE Journal of Solid-State Circuits, 2012,Volume: 47,Issue: 11,Page: 2763-2772
Authors:  Hegong Wei;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite | View/Download:13/0 | TC[WOS]:51 TC[Scopus]:0 | Submit date:2018/10/30
2-b-per-cycle (2 B/c)  Analog-to-digital Converter (Adc)  Resistive Dac  Successive Approximation Register (Sar)