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A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite  |  View/Download:31/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:20/0  |  Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)  
Metastablility in SAR ADCs Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017,Volume: 64,Issue: 2,Page: 111-115
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Boris Murmann;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:17/0  |  Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Comparator  Metastability  Successive Approximation Register (Sar)  
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction Conference paper
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 12-15 Sept. 2016
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 9,Page: 2196-2206
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Reference Noise  Successive-approximation-register (Sar) Adc  Thermal Noise  
A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS Conference paper
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, United states, 22-26 Feb. 2015
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite  |  View/Download:10/0  |  Submit date:2018/11/06
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US8659461B1, 申请日期: 2012-11-13, 公开日期: 2014-02-25
Authors:  Yan Zhu;  Chi Hang Chan;  Sai Weng Sin;  Seng Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite  |  View/Download:11/0  |  Submit date:2019/03/30
Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014,Volume: 22,Issue: 2,Page: 372-383
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:9/0  |  Submit date:2018/10/30
Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching  
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2013,Volume: 48,Issue: 8,Page: 1783-1794
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins
Favorite  |  View/Download:15/0  |  Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc