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Nano-Ampere Low-Dropout Regulator Designs for IoT Devices Conference paper
Authors:  Huang, Yuanqing;  Lu, Yan;  Maloberti, Franco;  Martins, Rui P.
Favorite | View/Download：37/0 | TC[WOS]:4 TC[Scopus]:7 | Submit date：2018/10/30
LDO regulator  output-capacitor-free LDO regulator  ultra-low quiescent LDO  dynamic current boosting  
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC Conference paper
Authors:  Wang, Guancheng;  Li, Cheng;  Zhu, Yan;  Zhong, Jianyu;  Lu, Yan;  Chan, Chi-Hang;  Martins, Rui P.
Favorite | View/Download：49/0 | TC[WOS]:0 TC[Scopus]:2 | Submit date：2018/10/30
Gain error calibration  testing signal generation  SAR ADC  bridge DAC  low-dropout (LDO) regulator  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite | View/Download：48/0 | TC[WOS]:2 TC[Scopus]:4 | Submit date：2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
An Inverse-Class-F CMOS VCO with Intrinsic-High-Q 1st-and 2nd-Harmonic Resonances for 1/f(2)-to-1/f(3) Phase-Noise Suppression Achieving 196.2dBc/Hz FOM Conference paper
Authors:  Lim, Chee-Cheow;  Yin, Jun;  Mak, Pui-In;  Ramiah, Harikrishnan;  Martins, Rui P.;  IEEE
Favorite | View/Download：10/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2018/10/30
A Dual-Output SC Converter with Dynamic Power Allocation for Multi-Core Application Processors Conference paper
Authors:  Jiang, Junmin;  Lu, Yan;  Liu, Xun;  Ki, Wing-Hung;  Mok, Philip K. T.;  Seng-Pan, U.;  Martins, Rui P.;  IEEE
Favorite | View/Download：16/0 | TC[WOS]:2 TC[Scopus]:0 | Submit date：2018/10/30
An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator Conference paper
Authors:  Huang, Mo;  Lu, Yan;  Seng-Pan, U.;  Martins, Rui P.
Favorite | View/Download：6/0 | TC[WOS]:18 TC[Scopus]:43 | Submit date：2018/10/30
Amplifier  analog assisted (AA)  coarse/fine tuning  digital control  fully integrated voltage regulator (FIVR)  limit cycle oscillation (LCO)  low-dropout (LDO) regulator  nonlinear control  output-capacitor-free  power management  
A 0.0056mm(2) All-Digital MDLL Using Edge Re-Extraction, Dual-Ring VCOs and a 0.3mW Block-Sharing Frequency Tracking Loop Achieving 292fs(rms) Jitter and-249dB FOM Conference paper
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.;  IEEE
Favorite | View/Download：12/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date：2018/10/30