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Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias  
Comparator with built-in reference voltage generation and split-ROM encoder for a high-speed flash ADC Conference paper
ISSCS 2015 - International Symposium on Signals, Circuits and Systems, Iasi, ROMANIA, JUL 09-10, 2015
Authors:  Chen Y.;  Mak P.-I.;  Yang J.;  Yue R.;  Wang Y.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/12