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60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | View/Download:31/0 | TC[WOS]:12 TC[Scopus]:0 | Submit date:2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
Design and experimental verification of a power effective Flash-SAR subranging ADC Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010,Volume: 57,Issue: 8,Page: 607-611
Authors:  U-Fat Chio;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins;  Franco Maloberti
Favorite | View/Download:24/0 | TC[WOS]:21 TC[Scopus]:0 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Digital Error Correction (Dec)  Flash Adc  Sar Adc  Subranging Adc  
A rapid power-switchable track-and-hold amplifier in 90-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010,Volume: 57,Issue: 1,Page: 16
Authors:  He-Gong Wei;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite | View/Download:16/0 | TC[WOS]:13 TC[Scopus]:0 | Submit date:2018/10/30
High-accuracy  High-speed  Power Switchable  Track-and-hold (T/h)