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A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 8,Page: 1966-1976
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, Rui P.;  Maloberti, Franco
Favorite | View/Download:44/0 | TC[WOS]:5 TC[Scopus]:8 | Submit date:2018/10/30
Analog-to-digital Converter (Adc)  Flash  Time-based Dual-edge-triggered  
A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS Journal article
Electronics Letters, 2016,Volume: 52,Issue: 16,Page: 1368-1370
Authors:  Yan Lu;  Cheng Li;  Yan Zhu;  Mo Huang;  Seng-Pan U;  Rui P. Martins
Favorite | View/Download:15/0 | TC[WOS]:14 TC[Scopus]:13 | Submit date:2019/02/11
Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite | View/Download:16/0 | TC[WOS]:5 TC[Scopus]:6 | Submit date:2019/02/11