UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-4 of 4 Help

Filters            
Selected(0)Clear Items/Page:    Sort:
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure Conference paper
2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 13-15 June 2012
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:16/0  |  Submit date:2019/02/11
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US20120229313A1, 申请日期: 2011-09-14, 公开日期: 2012-09-13
Authors:  Sai-Weng SIN;  He-Gong WEI;  Franco MALOBERTI;  Li DING;  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Seng-Pan U;  Rui Paulo da Silva MARTINS
Favorite  |  View/Download:9/0  |  Submit date:2019/02/26
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation Journal article
IEEE Journal of Solid-State Circuits, 2012,Volume: 47,Issue: 11,Page: 2614-2626
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite  |  View/Download:13/0  |  Submit date:2018/10/30
Decoupled Flip-around Mdac  Offset-cancellation  Pipelined-sar Adc  Vdd -attenuator