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A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS Conference paper
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, SOUTH KOREA, November 6-8, 2017
作者:  Wei Wang;  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U.;  Rui Paulo Martins
收藏  |  浏览/下载:15/0  |  提交时间:2019/02/11
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017,Volume: 52,Issue: 10,Page: 2576-2588
作者:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng;  Wei, Lai;  Seng-Pan, U.;  Martins, Rui Paulo
收藏  |  浏览/下载:17/0  |  提交时间:2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
A 0.0045-mm2 32.4-μW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2015,Volume: 62,Issue: 3,Page: 246-250
作者:  Zushu Yan;  Wei Wang;  Pui-In Mak;  Man-Kay Law;  Rui P. Martins
收藏  |  浏览/下载:14/0  |  提交时间:2019/02/11
Capacitive Load  Capacitor Multiplier  Cmos  Frequency Compensation  Stability  Two-stage Amplifier  
Micropower two-stage amplifier employing recycling current-buffer Miller compensation Conference paper
2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, AUSTRALIA, JUN 01-05, 2014
作者:  Wei Wang;  Zushu Yan;  Pui-In Mak;  Man-Kay Law;  Rui P. Martins
收藏  |  浏览/下载:9/0  |  提交时间:2019/02/11
Cascade Analog to Digital Converting System Patent
专利类型: 发明专利, 专利号: US8466823B2, 申请日期: 2011-08-05, 公开日期: 2013-06-18
作者:  U-Fat CHIO;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
收藏  |  浏览/下载:9/0  |  提交时间:2019/03/06
Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption Patent
专利类型: 发明专利, 专利号: US8427355B2, 申请日期: 2011-09-14,
作者:  Sai-Weng Sin;  Li Ding;  Yan Zhu;  He-Gong Wei;  Chi-Hang Chan;  U-Fat Chio;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
收藏  |  浏览/下载:6/0  |  提交时间:2019/03/30
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US20120229313A1, 申请日期: 2011-09-14, 公开日期: 2012-09-13
作者:  Sai-Weng SIN;  He-Gong WEI;  Franco MALOBERTI;  Li DING;  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Seng-Pan U;  Rui Paulo da Silva MARTINS
收藏  |  浏览/下载:7/0  |  提交时间:2019/02/26
Design and experimental verification of a power effective Flash-SAR subranging ADC Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010,Volume: 57,Issue: 8,Page: 607-611
作者:  U-Fat Chio;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins;  Franco Maloberti
收藏  |  浏览/下载:21/0  |  提交时间:2019/02/11
Analog-to-digital Converter (Adc)  Digital Error Correction (Dec)  Flash Adc  Sar Adc  Subranging Adc  
A rapid power-switchable track-and-hold amplifier in 90-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010,Volume: 57,Issue: 1,Page: 16
作者:  He-Gong Wei;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
收藏  |  浏览/下载:13/0  |  提交时间:2018/10/30
High-accuracy  High-speed  Power Switchable  Track-and-hold (T/h)  
Linearity analysis on a series-split capacitor array for high-speed SAR ADCs Conference paper
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, Knoxville, TN, AUG 10-13, 2008
作者:  Yan Zhu;  U-Fat Chio;  He-Gong Wei;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
收藏  |  浏览/下载:18/0  |  提交时间:2019/02/11