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Split-based time-interleaved ADC with digital background timing-skew calibration Conference paper
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, Italy, JUN 12-15, 2017
Authors:  Guo M.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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Adc  Converters  Digital Background Calibration  Split-adc  Time-interleaving  Timing  
Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016,Volume: 63,Issue: 9,Page: 903-907
Authors:  Huang M.;  Lu Y.;  Sin S.-W.;  Seng P.;  Martins R.P.;  Ki W.-H.
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Compensation Zero  Describing Function  Digital Control  Feedforward Path  Limit Cycle Oscillation (Lco)  Low Dropout Regulator (Ldo)  Sampled Nonlinear System  
A high resolution multi-bit incremental converter insensitive to DAC mismatch error Conference paper
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Lisbon, Portugal, JUN 27-30, 2016
Authors:  Biao Wang;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
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High Resolution  Incremental Converter  Multi-bit Quantizer  Insensitive To Dac Mismatch  
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 7,Page: 2603-2607
Authors:  Jianwei Liu;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
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Background Linearity Calibration  Splitdigital- To-analog Converter (Dac)  Successive Approximation Register (Sar) Adc  Uniform Quantization Theory (Uqt)  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
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Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
Cascade Analog to Digital Converting System Patent
专利类型: 发明专利, 专利号: US8466823B2, 申请日期: 2011-08-05, 公开日期: 2013-06-18
Authors:  U-Fat CHIO;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
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A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
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Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators Conference paper
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, Jeju, South Korea, 14-16 Nov. 2011
Authors:  Wong S.-S.;  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc  Flash Adc  Sar Adc  
A power effective 5-bit 600 MS/s binary-search ADC with simplified switching Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Wong S.S.;  Chio U.-F.;  Choi H.-L.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
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Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc  
Comparator-based successive folding ADC Conference paper
1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009, Shanghai, PEOPLES R CHINA, NOV 19-21, 2009
Authors:  Chio U.-F.;  Choi H.-L.;  Chan C.-H.;  Wong S.-S.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11