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A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite  |  View/Download:14/0  |  Submit date:2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration Conference paper
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Toyama, JAPAN, NOV 07-09, 2016
Authors:  Qiu L.;  Kai T.;  Zhu Y.;  Siek L.;  Zheng Y.;  Seng-Pan U.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/14
Sar Adcs  Time Skew Calibration  Time-interleaved  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration